Due to the extremely advanced nature of today's electric technique, the electronics industry provides various products with more complicated and more humanistic functionality. The recent trends of electric products are towards light, thin and compact. Numerous improvements within electric technique have been made in recent years to meet the requirements for microminiaturization and speedy operation, so that a plurality of chips are vertically stacked on a substrate to obtain a great capacity with several times or a requirement with more functions as well as sealed in a package, which may be called multi-chip stack package. Nevertheless, the plural chips are sealed with an encapsulant while performing multi-chip stack packaging process formerly and then various electrical tests are performed after encapsulated. If a chip only among the multi-chip stack package cannot operate normally, it results in that the entire semiconductor package couldn't work normally and is unable to be fixed after encapsulated.
Referring to FIG. 1, a conventional multi-chip stack package primarily comprises a substrate 100, a first chip 10, a second chip 20, a plurality of bonding wires 31 and 32 and an encapsulant 40. According to FIG. 2, the substrate 100 includes a plurality of wire-bonding fingers 110 and a plurality of traces 120 formed on an inner surface 101 of the substrate 100, where the wire-bonding fingers 110 are adjacent to a die-attaching area 103 of the substrate 100. The first chip 10 is attached onto the die-attaching area 103 and the second chip 20 is stacked above the first chip 10. Referring again to FIGS. 1 and 2, the wire-bonding fingers 110 formed on the inner surface 101 are exposed on an insulation layer 130 of the substrate 100 for wire-bonding connection. A plurality of external contact pads 140 are formed on an outer surface 102 of the substrate 100. The first chip 10 has a plurality of first bonding pads 11, which are electrically connected with the corresponding wire-bonding fingers 110 via the first bonding wires 31. An interposer 12 is disposed between the first chip 10 and the second chip 20. The second chip 20 has a plurality of second bonding pads 21, which are electrically connected with the wire-bonding fingers 110 via the second bonding wires 32. Accordingly, the wire-bonding fingers 110 utilizing an identical signal or common power/ground may be connected with a first bonding wire 31 and a second bonding wire 32 simultaneously (as shown in FIG. 2).
The known multi-chip stack package mentioned above may further comprise an encapsulant 40 to seal the first chip 10 and the second chip 20 to be applicable for memory cards or BGA packages. Sometimes, there has had faults in chips or connecting bonding wires thereof during semiconductor packaging processes, but the encapsulated chips are not rework-able when they had been tested to find out which one or portion of them cannot operate normally after packaged. The entire multi-chip stack package is unable to work normally if only one or portion of chips and/or bonding wires has trouble and has been sealed and electrically connected with substrate to involve other good chips in failure, must be discarded resulting in high scrapped rate.
There are several methods to solve the problem mentioned above at present and one of them is to perform completed electrical function tests for all chips in wafer level to identify KGD (Known Good Die) or not, but the cost for this test is too expensive to apply for mass production in low cost. Another method is to provide a fix step during semiconductor packaging processes, which is disclosed in R.O.C. Taiwan Patent publication No. 409,330 titled “repairable multi-chip module package”. A test is performed during die-attaching process and electrically connecting process after finishing lower-layer chip assembly but prior to encapsulation process to identify the lower-layer chips are bad or not. When chip qualities are confirmed, and then a repairing step is executed. The bonding wires connecting with bad chip(s) are removed and then a substitute chip (KGD) is attached above the bad chip. However, since this repairing method needs to provide an on-line test and removal of the bonding wires connecting with bad chips on lower layer prior to encapsulation process, the quality after encapsulation process is still uncertain and there are extra limitations in the fabricating processes. Besides, the stack method that the good chip are stacked above the bad chips is not reserved for the use of multi-chip stack package.